Semiconductor Package with Lead Tip Inspection Feature

ABSTRACT

A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices each of the sidewall-facing terminals is electrically connected to the semiconductor die of the respective packaged semiconductor device. Each of the sidewall-facing terminals of each packaged semiconductor device is provided from the electrically conductive material formed within the gaps.

BACKGROUND

Leadless semiconductor packages are designed with terminals that aresubstantially coextensive with the encapsulant body. Examples ofleadless semiconductor packages include DFN (dual flat no leads) and QFN(quad flat no leads) packages, to name a few. Leadless semiconductorpackages offer notable advantages over leaded packages including a smallfootprint and low material cost. However, the I/O density of thesepackages is constrained by minimum spacing between conductive bond padsand the areal footprint of the encapsulant body. In many applications,there is a need to reduce device size while simultaneously maintainingor increasing the I/O density of the device. It is therefore desirableto provide a leadless package with an increased I/O capability for agiven areal footprint.

SUMMARY

A method of forming a semiconductor device is disclosed. According to anembodiment, the method includes providing a carrier, mounting aplurality of semiconductor dies on the carrier, forming a region ofelectrically insulating encapsulant material on the carrier that coverseach of the semiconductor dies, removing sections of the encapsulantmaterial to form gaps in the region of electrically insulatingencapsulant material between each of the semiconductor dies, formingelectrically conductive material within the gaps, and singulating theregion of electrically insulating encapsulant material along each of thegaps to form a plurality of discrete encapsulant bodies. Each of thepackaged semiconductor devices comprises a sidewall-facing terminal thatis disposed on a sidewall of the encapsulant body. For each of thepackaged semiconductor devices the sidewall-facing terminal iselectrically connected to the semiconductor die of the respectivepackaged semiconductor device. The sidewall-facing terminal of eachpackaged semiconductor device is provided from the electricallyconductive material formed within the gaps.

Separately or in combination, for each of the packaged semiconductordevices the sidewall-facing terminal extends completely between top andbottom surfaces of the encapsulant body.

Separately or in combination, after singulating the region ofelectrically insulating encapsulant material, each of the packagedsemiconductor devices comprises a notch in the sidewall of theencapsulant body that extends between the top and bottom surfaces, andfor each of the packaged semiconductor devices, the sidewall-facingterminal is disposed within the notch.

Separately or in combination, the method further comprises performing afurther cutting step after singulating the region of electricallyinsulating encapsulant material such that the sidewall of theencapsulant body is substantially coplanar to the sidewall-facingterminal.

Separately or in combination, for each of the packaged semiconductordevices the sidewall-facing terminal is part or a conductive region thatcontinuously extends from the sidewall to one or both of the top andbottom surfaces of the encapsulant body.

Separately or in combination, the encapsulant material comprises alaser-activatable mold compound, and forming the electrically conductivematerial within the gaps comprises applying a laser on the laseractivatable mold compound thereby forming a laser activated surface inthe laser activatable mold compound, and performing a plating processthat selectively forms the electrically conductive material in the laseractivated surface.

Separately or in combination, forming the region of electricallyinsulating encapsulant material comprises encapsulating each of thesemiconductor dies with a first mold compound material, and forming thelaser-activatable mold compound on the first mold compound material suchthat the laser-activatable mold compound is exposed at outer surfaces ofthe discrete encapsulant bodies.

Separately or in combination, the plating process is an electroplatingprocess.

Separately or in combination, the plating process is an electrolessplating process.

Separately or in combination, each of the semiconductor dies comprises aplurality of conductive terminals disposed on a main surface, and a rearsurface opposite from the main surface, and wherein the semiconductordies are each mounted on the carrier such that the main surface facesaway from the carrier.

Separately or in combination, each of the semiconductor dies comprises amain surface with a plurality of bond pads and a rear surface oppositefrom the main surface, wherein the semiconductor dies are each mountedon the carrier such that the main surface faces the carrier.

Separately or in combination, the method further comprises removing thecarrier from the region of electrically insulating encapsulant andtransferring the region of electrically insulating encapsulant materialto a transfer laminate before removing the sections of the encapsulantmaterial, and the removing sections of the encapsulant material and theforming of the electrically conductive material are performed with theregion of electrically insulating encapsulant material being disposed onthe transfer laminate.

A packaged semiconductor device is disposed. According to an embodiment,the packaged semiconductor device includes a semiconductor diecomprising a plurality of bond pads, an encapsulant body of electricallyinsulating encapsulant material that encapsulates the semiconductor die,a sidewall-facing terminal disposed on a sidewall of the encapsulantbody, the sidewall-facing terminal is electrically connected to one ofthe bond pads; the sidewall-facing terminal extends completely betweentop and bottom surfaces of the encapsulant body, and the electricallyinsulating encapsulant material comprises a laser activatable moldcompound.

Separately or in combination, the sidewall-facing terminal continuouslyextends from the sidewall of the encapsulant body to a main surface ofthe encapsulant body that intersects with the sidewall of theencapsulant body.

Separately or in combination, the packaged semiconductor devicecomprises a notch in the sidewall of the encapsulant body that extendsbetween the top and bottom surfaces, and wherein the sidewall-facingterminal is disposed within the notch.

Separately or in combination, the packaged semiconductor device of claim14, wherein the sidewall-facing terminal is substantially coplanar tothe sidewall of the encapsulant body.

Separately or in combination, the packaged semiconductor device isconfigured as an integrated circuit.

Separately or in combination, the encapsulant body comprises a firstmold compound material that encapsulates the semiconductor die, andwherein the laser-activatable mold compound is formed on the first moldcompound material such that the laser-activatable mold compound isexposed at outer surfaces of the encapsulant body.

Separately or in combination, a rear surface of the semiconductor die isexposed at the bottom surface of the encapsulant body.

Separately or in combination, a rear surface of the semiconductor die iscovered by the encapsulant body.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

The elements of the drawings are not necessarily to scale relative toeach other. Like reference numerals designate corresponding similarparts. The features of the various illustrated embodiments can becombined unless they exclude each other. Embodiments are depicted in thedrawings and are detailed in the description which follows.

FIG. 1 , which includes FIGS. 1A-1H, depicts method steps of forming apackaged semiconductor device, according to an embodiment. FIGS. 1A-1Fdepict method steps from a cross-sectional perspective and FIG. 1G-1Hdepict the packaged semiconductor device from an isometric perspective.

FIG. 2 , which includes FIGS. 2A-2F, depicts method steps of forming apackaged semiconductor device, according to an embodiment, according toan embodiment.

FIG. 3 , which includes FIGS. 3A-3F, depicts method steps of forming apackaged semiconductor device, according to an embodiment, according toan embodiment.

FIG. 4 depicts a packaged semiconductor device from an isometricperspective, according to an embodiment.

FIG. 5 depicts a packaged semiconductor device from an isometricperspective, according to an embodiment.

FIG. 6 , which includes FIGS. 6A and 6B, depicts an assembly of twopackaged semiconductor devices mounted on a circuit board, according toan embodiment. FIG. 6A depicts the assembly from a plan-viewperspective. FIG. 6B depicts the assembly from a side-view perspective.

FIG. 7 , which includes FIGS. 7A and 7B, depicts an assembly of twopackaged semiconductor devices mounted on a circuit board, according toan embodiment. FIG. 7A depicts the assembly from an isometric viewperspective. FIG. 7B depicts the assembly from a side-view perspective.

DETAILED DESCRIPTION

The embodiments described herein include a molded semiconductor packagewith terminals formed along the sidewalls of the encapsulant body. Thesesidewall-facing terminals are formed by a laser structuring technique.According to this technique, the encapsulant body of the packageincludes laser activatable mold compound that is selectively activatedto activate surface metals by application of laser. Conductive materialis formed in the laser activated region by a plating process such aselectroplating or electroless plating. Using this advantageoustechnique, the sidewall-facing terminals can be formed to extend acrossa complete thickness of the encapsulant body. These sidewall-facingterminals can serve as LTI (lead tip inspection) features to inspect theintegrity of a solder connection. In addition, or in the alternative,these sidewall-facing terminals can be configured as separate contactpoints for direct electrical connection.

Referring to FIG. 1 , selected method steps for forming a semiconductorpackage are depicted, according to an embodiment. Referring to FIG. 1A,a carrier 100 is provided. Generally speaking, the carrier 100 can beany structure that is compatible with batch processing techniques forsemiconductor devices. For example, the carrier can be a large metalpanel that is capable of accommodating tens or hundreds of semiconductordies, e.g., an 18″×24″ panel. In an embodiment, the carrier 100 includesa conductive metal, e.g., copper, aluminum, etc.

Multiple semiconductor dies 102 are mounted on the carrier 100. Whilethe figure depicts four of the semiconductor dies 102 mounted on thecarrier 100, in principle the methods described herein can be used withany plurality of dies (i.e., two or more dies) to form multiple packagedsemiconductor devices simultaneously. The semiconductor dies 102 canhave a wide variety of device configurations. For example, thesemiconductor dies 102 can be configured as discrete switching devices,e.g., MOSFETs (metal oxide semiconductor field effect transistors),IGBTs (insulated gate bipolar transistors), HEMTs (high electronmobility transistors), etc. The semiconductor dies 102 can also beconfigured as integrated devices, e.g., controllers, processors,sensors, amplifiers, etc.

Each semiconductor die 102 includes a plurality of conductive bond pads104 that provide I/O terminals of the device, e.g., gate, source, drain,collector, emitter, etc. According to an embodiment, verticalinterconnect structures 106 are formed on the bond pads 104. Thesevertical interconnect structures 106 elevate the point of electricalcontact to the I/O terminals of the device above the main surface of thesemiconductor dies 102. The vertical interconnect structures 106 caninclude electrically conductive materials such as copper, gold,aluminium, nickel, etc., and alloys thereof, and solder materials. Thevertical interconnect structures 106 may be wire stud bumps or metalpillars, for example.

The semiconductor dies 102 are mounted on the carrier 100 with a mainsurface 101 of the dies 102 facing away from the carrier 100. Hence, thebond pads 104 of the semiconductor dies 102 face away from the carrier100. Rear surfaces 103 of the dies 102 are affixed to the carrier 100 byan adhesive material. In the embodiment of FIG. 1A, an adhesive tape 108is used to affix the dies 102 to the carrier. The adhesive tape 108 maybe a plasticized PVC film, for example.

Referring to FIG. 1 B, a region of electrically insulating encapsulantmaterial 110 is formed on the carrier 100. The region of electricallyinsulating encapsulant material 110 may be formed using any of a varietyof molding techniques, e.g., injection molding, transfer molding,compression molding, etc. The region of electrically insulatingencapsulant material 110 is formed such that the main surface 101 ofeach semiconductor die 102 is covered by the encapsulant material. As aresult, each of the semiconductor dies 102 is embedded within theencapsulant material.

According to an embodiment, the region of electrically insulatingencapsulant material 110 is formed such that the vertical interconnectstructures 106 are exposed at an upper surface of the encapsulantmaterial. This may be done using two-step process wherein the region ofelectrically insulating encapsulant material 110 is initially formed toinclude an upper surface that is above the vertical interconnectstructures 106 and the upper surface is locally thinned, e.g.,polishing, grinding, etching, etc., to expose upper ends of the verticalinterconnect structures 106. Alternatively, the vertical interconnectstructures 106 may be exposed from the encapsulant material byperforming a one-step molding process wherein the mold chamber isconfigured to form an upper surface of the encapsulant material that isbelow upper ends of the vertical interconnect structures 106.

The region of electrically insulating encapsulant material 110 is formedto include laser-activatable mold compound. As used herein,“laser-activatable mold compound” refers to a mold compound thatincludes at least one additive, e.g., in the form of a metal oxide(spinel type) which is activated by a focused laser beam to become anactive metal for a subsequent electroless or electroplating processing.In addition to the additive, a “laser-activatable mold compound”includes a polymer material as a base material. Examples of thesepolymers include thermoset polymers having a resin base, ABS(acrylonitrile butadiene styrene), PC/ABS (polycarbonate/acrylonitrilebutadiene styrene), PC (polycarbonate), PA/PPA(polyimide/polyphthalamide), PBT (polybutylene terephthalate), COP(cyclic olefin polymer), PPE (polyphenyl ether), LCP (liquid-crystalpolymer), PEI (polyethylenimine or polyaziridine), PEEK (polyether etherketone), PPS (polyphenylene sulfide), etc.

According to an embodiment, the region of electrically insulatingencapsulant material 110 is formed to include both laser-activatablemold compound and non-laser-activatable mold compound, i.e., moldcompound that is devoid of laser activated metal additives. For example,the region of electrically insulating encapsulant material 110 may beformed by a two-step process. In a first step, each of the semiconductordies 102 is encapsulated by a first mold material. The first moldmaterial may include a polymer material, e.g., epoxy materials,thermosetting plastics, etc. The first mold material is formed as aninterior encapsulant body that surrounds the semiconductor die 102. In asecond step, the laser-activatable mold compound is formed around theinterior encapsulant body. As a result, the laser-activatable moldcompound is present at the upper surface of the region of electricallyinsulating encapsulant material 110 and in lateral regions between eachof the semiconductor dies 102.

Referring to FIG. 1C, sections of the encapsulant material are removed.This may be done using techniques such as etching or drilling. Removingthese sections forms gaps (i.e., trench like structures) 112 in theencapsulant material between each of the semiconductor dies 102.According to an embodiment, the gaps 112 are formed to fully extendthrough the region of electrically insulating encapsulant material 110thereby exposing the adhesive tape 108 and/or the carrier 100. The gaps112 may be formed in a lateral pattern along a single cross-sectionalplane. The view of FIG. 1C illustrates one cross-sectional plane thatruns through a center of the gaps. In another cross-sectional plane thatis parallel to and offset from this cross-sectional plane, the regionsbetween the semiconductor dies 102 may be filled with encapsulantmaterial, e.g., in a similar manner as shown in FIG. 1B. From aplan-view perspective, the gaps 112 may be formed in a crisscrosspattern that encloses each semiconductor die 102 by a plurality of thegaps 112 on each side.

Referring to FIG. 1D, electrically conductive material 114 is formed onthe encapsulant material. Specifically, electrically conductive material114 is formed on an upper surface of the encapsulant material that isopposite from the carrier 100. This electrically conductive material 114is structured into a main-surface-facing terminal 116 which contacts oneof the vertical interconnect structures 106. Additionally, theelectrically conductive material 114 is formed in the gaps 112.Specifically, the electrically conductive material 114 is formed along asidewall of the encapsulant material that faces the gaps 112. Thiselectrically conductive material 114 is structured into asidewall-facing terminal 118. The sidewall-facing terminals 118 can alsobe electrically connected to the semiconductor die. For example, thesidewall-facing terminals 118 can be part of a continuous electricallyconductive structure which includes the main-surface-facing terminal 116and contacts the vertical interconnect structures 106, e.g., as shown inthe depicted embodiment. Alternatively, a conductive connector, e.g.,clip, wire, etc. may be provided within the encapsulant body to form anelectrical connection between the sidewall-facing terminals 118 and thesemiconductor dies 102.

According to an embodiment, the electrically conductive material 114 isformed on the region of encapsulant material 110 using a laserstructuring process. Advantageously, this laser structuring processprovides a great degree of flexibility with regard to the location andstructure of the electrically conductive material 114. Specifically, theabove described structures including the main-surface-facing terminal116 and the sidewall-facing terminals 118 would be difficult orimpossible to form with the geometries disclosed herein usingconventional techniques due to the requisite degree of precision neededto form these structures in small areas.

The laser structuring process includes a laser activation step. Thelaser activation step is performed by directing a laser beam on theselected regions of the laser-activatable mold compound. The energy fromthe laser beam creates laser-activated regions in the encapsulant body.The laser-activated regions include metal complexes present at thesurface of the laser-activatable mold compound and are capable of actingas a nuclei for metal plating process, examples of which will bedescribed in further detail below. By contrast, the portions of thelaser-activatable mold compound that are not exposed to a laser beam donot have exposed metal complexes that are capable of acting as a nucleiduring a metal plating process.

The plating process selectively forms conductive material in thelaser-activated regions of the mold compound without substantiallyforming the conductive material in inactivated regions of thelaser-activatable mold compound. This means that the vast majority ofmetal (e.g., greater than 95%, 99% etc.) formed by the plating processforms in the laser-activated regions. Moreover, the conductive materialformed in the laser-activated regions forms a defined, conductive trackor pad in the encapsulant body. Generally speaking, the plating processmay be any metal plating process that utilizes a seed metal as a basisfor depositing metal thereon. These plating processes includeelectroless plating process and electroplating processes.

According to an embodiment, the plating process is an electrolessplating process. According to this technique, the semiconductor deviceis submerged in a chemical bath that contains metal ions (e.g., Cu+ions, Ni+ ions, Ag+ ions, etc.) that react with the organic metalcomplexes in the later activated regions, thereby forming a completelayer of the element from the chemical bath. The plating process maybegin with a cleaning step to remove laser debris and may be followed byan additive build-up of plated metal using the chemical bath.Optionally, additional metal coatings e.g., coatings containing Ni, Au,Sn, Sn/Pb, Ag, Ag/Pd, etc., may be applied on the deposited metal afterthe plating process.

Referring to FIG. 1E, the carrier 100 is removed. This may be done usinga chemical etching technique, for example. The adhesive tape 108 may beremoved as well. As a result, a lower surface of the region ofelectrically insulating encapsulant material 110 is exposed. At thisstage, the region of electrically insulating encapsulant material 110remains intact by bridge portions 120 of the encapsulant material thatare between each of the gaps 120. The cross-sectional view of FIG. 1E istaken along a cross-sectional plane different from that of FIG. 1D whichextends through the bridge portions 120.

Referring to FIG. 1F, a singulation process is performed. Thesingulation process may be performed by transferring the region ofelectrically insulating encapsulant material 110 to a a temporarycarrier 122, which may be a laminate transfer carrier, for example.Subsequently, the region of electrically insulating encapsulant material110 is singulated along cutting planes 123 which extend along the gaps112 and through the bridge portions 120 of the encapsulant material. Asa result, a plurality of discrete encapsulant bodies are formed. Theregion of electrically insulating encapsulant material 110 may besingulated according to any of a variety of dicing techniques, e.g.,mechanical cutting or sawing, chemical cutting, laser ablation, etc.

Referring to FIG. 1G, an example of a semiconductor package 200 that isproduced after performing the singulation process of FIG. 1F isdepicted, according to an embodiment. This semiconductor package 200includes an encapsulant body 202 with sidewalls 204 that extends betweena top surface 206 of the encapsulant body 202 and a bottom surface ofthe encapsulant body 202 (not shown). The encapsulant body 202 includesnotches (i.e., recessed regions) 208 in the sidewalls 204. The notches208 result from cutting the region of electrically insulatingencapsulant material 110 along the cutting plane 123 which extendsthrough a center of the gaps 112, as shown in FIG. 1F. Thesidewall-facing terminals 118 are disposed within these notches 208. Thesidewall-facing terminals 118 may cover each surface of the notches 208.For instance, the notches 208 may have a three-sided configuration withtwo outer walls that face one another and an interior wall that isspaced apart from the sidewalls 204. Each of these surfaces may beactivated during the laser activation step, and hence thesidewall-facing terminals 118 may be disposed along each of theseinterior surfaces of the notches 108.

Referring to FIG. 1H, a further cutting step has been performed toeliminate the notches 208 in the sidewalls 204 of the encapsulant body202. This may be done by selecting the cutting plane of the furthercutting step to be parallel to the sidewalls 204 and coincides with aninner face of the notches 208. The further cutting step can be performedby mechanical cutting or sawing, chemical cutting, laser ablation, etc.This further cutting step can be performed on the same temporary carrier122 as the step FIG. 1F or may be performed after transferring theencapsulant bodies to another carrier.

The further cutting step of FIG. 1H is optional. In some cases, thenotches 208 in the encapsulant body 202 may be acceptable or preferred.For instance, it may be preferable to maintain the notches 208 toenhance adhesion with a solder material. In that case, the furthercutting step of FIG. 1H may be omitted so that the package 200 of FIG.1G represents the final product. Alternatively, it may be preferable toeliminate the notches 208 to provide a side of the package that can beplaced flush against another surface. In that case, the further cuttingstep may be performed so that the package 200 of FIG. 1H represents thefinal product.

Referring to FIG. 2 , selected method steps for forming a moldedsemiconductor package are depicted, according to an embodiment. Theprocessing steps of FIG. 2 may be substantially the same or similar asthe corresponding process steps of FIG. 1 , with the followingexceptions. As shown in FIG. 2A, instead of using an adhesive tape 108,each of the semiconductor dies 102 is mounted on the carrier 100 byproviding a die attach material 124 such as conductive or non-conductiveglue between the rear surface 103 of each semiconductor die 102 and thecarrier 100. The die attach material 124 is formed such that portions ofthe carrier 100 between each semiconductor die 102 are exposed.Subsequently, as shown in FIGS. 2B and 2C, the region of electricallyinsulating encapsulant material 110 is formed and the gaps 112 areformed in the region of electrically insulating encapsulant material110, e.g., in a similar manner as previously described. Subsequently, asshown in FIG. 2D, the electrically conductive material 114 is formed onthe encapsulant material. The electrically conductive material 114 maybe formed by a laser structuring process. According to an embodiment,this laser structuring process includes the laser activation stepdescribed above followed by an electroplating process. Electroplatingrefers to any process in which electrical current is used to form a thinmetal coating on the exterior surfaces of an electrified element.According to this technique, the device and a cathode are submerged inan aqueous based solution, and a potential difference is created betweenthe submerged cathode and a submerged conductive article (which acts asan anode). In this case, the metal complexes present at the surface ofthe laser-activatable mold compound act as the anode. Additionally, theportion of the carrier 100 that is exposed from the die attach material124 acts as an anode. Dissolved metal ions from the cathode form areattracted to the cathode and thereby form a deposited region ofconductive metal, e.g., copper. As can be seen, the electroplatingprocess completely fills the gaps 112 in the encapsulant material.Subsequently, as shown in FIGS. 2E and 2F, the carrier 100 is removedand the singulation process is performed, e.g., in a similar manner aspreviously described. In this case, the sidewall-facing terminal 118 iscoplanar to the sidewall of the encapsulant material after the initialcutting step. Thus, a further cutting step, e.g., as described withreference to FIG. 1H, may be omitted.

Referring to FIG. 3 , selected processing steps for forming a packagedsemiconductor device are depicted, according to another embodiment. Theprocessing steps of FIG. 3 may be substantially the same or similar asthe corresponding process steps of FIG. 1 , with the followingexceptions. As shown in FIG. 3A, the semiconductor dies 102 are eachmounted on the carrier 100 such that the main surface 101 of each diefaces the carrier 100. Thus, the conductive terminals of thesemiconductor die (vertical interconnect structures 106 in this example)adhere to the adhesive tape 108 and the rear surface 103 of thesemiconductor die 102 faces away from the carrier 100. Referring to FIG.3B, the region of electrically insulating encapsulant material 110 isformed. Referring to FIG. 3C, the carrier 100 and the adhesive tape 108are removed, e.g., in the manner previously described. Subsequently, theassembly including the region of electrically insulating encapsulantmaterial 110 and the semiconductor dies 102 is placed on a transferlaminate 126. The orientation of the assembly is flipped such that therear surfaces 103 of the semiconductor dies face away from thesubstrate. Subsequently, as shown in FIGS. 3D-3F, the gaps 112 areformed in the region of electrically insulating encapsulant material110, the regions of conductive material 114 are formed, and thesingulation process is performed, e.g., in a similar manner aspreviously described.

The method described with reference to FIG. 3 may be used to produce asemiconductor package wherein a rear surface 103 of the semiconductordie 102 is exposed at the bottom surface of the encapsulant body. Thispackage configuration may be preferable in certain applications, e.g.applications with rear-side cooling and/or vertical deviceconfigurations. The method described with reference to FIGS. 1-2 may beused to produce a semiconductor package wherein a rear surface 103 ofthe semiconductor die 102 is covered by the encapsulant body. Thispackage configuration may be preferable in certain applications, e.g.,lateral device configurations.

Referring to FIG. 4 , a semiconductor package 200 is depicted, accordingto an embodiment. The semiconductor package 200 may be formed accordingto any of the techniques described with reference to FIGS. 1-3 . Thesemiconductor package 200 includes an encapsulant body 202 withsidewalls 204 that extend between a top surface 206 of the encapsulantbody 202 and a rear surface of the encapsulant body 202 (not shown). Inthis context, the terms “top surface” and “rear surface” are used forexplanation purposes only to describe opposite faces of the encapsulantbody 202. In practice, the semiconductor package 200 may be arranged indifferent directions such that the “top surface” may face upward,downward, and to the side. The encapsulant body 202 may includelaser-activatable mold compound. The semiconductor package 200 includesa number of main-surface-facing terminals 116 disposed on the topsurface 206 of the encapsulant body 202 and a number of sidewall-facingterminals 118 disposed on the sidewalls 204 of the encapsulant body 202.In an embodiment, the rear surface of the encapsulant body 202 includesconductive terminals having the same configuration as themain-surface-facing terminals 116. In that case, the top surface 206 ofthe encapsulant body 202 and the rear surface of the encapsulant body202 can each be used as an interfacing surface with another article,e.g., a printed circuit board or other packaged device. Thisconfiguration may be obtained by further process steps of removing theregion of electrically insulating encapsulant material 110 from thecarrier 100 or from the temporary carrier 122 and performing furtherlaser activation and plating steps according to the techniques describedherein.

In the depicted embodiment, the sidewall-facing terminals 118 extendcompletely between the top surface 206 of the encapsulant body 202 andthe rear surface of the encapsulant body 202. That is, thesidewall-facing terminals 118 extend along a complete thickness of theencapsulant body 202. This terminal configuration has notableadvantages. Specifically, the sidewall-facing terminals 118 arewell-suited for LTI (lead tip inspection). LTI features allow foroptical inspection of a solder joint when the semiconductor package 200is mounted and electrically connected to an external apparatus, such asa printed circuit board. Because the sidewall-facing terminals 118extend along a complete thickness of the encapsulant body 202, a largearea is available for lead tip inspection of a solder joint that extendsup the side of the package. Additionally, the sidewall-facing terminals118 provide additional electrical contact points that are directlyaccessible for electrical connection when the semiconductor package 200is mounted and electrically connected to an external apparatus, such asa printed circuit. Examples of these configurations will be described infurther detail below with reference to FIGS. 6 and 7 .

In the depicted embodiment, the sidewall-facing terminals 118 and themain-surface-facing terminals 116 are part of one conductive structurethat continuously extends from the sidewall of the encapsulant body 202to the main surface 101 of the encapsulant body 202. As a result, thisone conductive structure provides an I/O terminal at two different sidesof the semiconductor package 200.

Referring to FIG. 5 , a semiconductor package 200 is depicted, accordingto another embodiment. The semiconductor package 200 is configured as adiscrete switching device, e.g., a power transistor such as a MOSFET,IGBT, etc. In this case the semiconductor package 200 includes firstterminal 208, which is collectively provided by one of the main-surfacefacing terminals 116 and one of the sidewall-facing terminals 118, asecond terminal 210, and a third terminal 212, which are each providedby one of the sidewall-facing terminals 118. By forming the second andthird terminals 210, 212 only on the sidewall, the first terminal 208can be made very large, which is beneficial for cooling and/orconduction. By contrast, the second and third terminals 210, 212 can besmaller terminals with lower conduction requirements. To this end, thefirst terminal 208 may be a large current carrying or heat generatingterminal (e.g., source or drain), whereas the second and third terminals210, 212 can be the remaining gate, source or drain terminals of thedevice.

Referring to FIG. 6 , an assembly 300 that includes two semiconductorpackages 200 mounted on a printed circuit board 302 is depicted,according to an embodiment. These semiconductor packages 200 may beformed according to any of the techniques described with reference toFIGS. 1-3 . While the two packages 200 are identical to one another inthe depicted embodiment, in principle this concept is applicable to anytwo semiconductor packages having the sidewall-facing terminals 118formed by the techniques described with reference to FIGS. 1-3 .

In the embodiment of FIG. 6 , each of the semiconductor package 200 aremounted such that main-surface facing terminals 116 face the printedcircuit board 302. The main-surface-facing terminals 116 areelectrically connected to bonding pads of the printed circuit board 302by solder joints 304. Further, the assembly 300 includes a directelectrical connection 306 between the sidewall-facing terminals 118 oftwo adjacent semiconductor packages 200. In the depicted embodiment,this direct electrical connection 306 is provided by a region of soldermaterial. More generally, the direct electrical connection 306 can beprovided by any of a variety of electrical connectors, e.g., wires,clips, etc. Advantageously, by providing the direct electricalconnection 306 between the two adjacent semiconductor packages 200 thatis above the printed circuit board 302, the need for a conductive trackwithin the circuit board to effectuate this connection is eliminated.Thus, the I/O connection density of the assembly 300 is advantageouslyimproved.

Referring to FIG. 7 , an assembly 300 that includes two semiconductorpackages 200 mounted on a printed circuit board 302 is depicted,according to an embodiment. The semiconductor packages 200 may be formedaccording to any of the techniques described with reference to FIGS. 1-3. In this embodiment, the semiconductor packages 200 are mounted withone of the sidewalls 204 facing the printed circuit board 302 and withthe sidewall-facing terminals 118 of each semiconductor package 200vertically spaced apart from one another. In this arrangement, themain-surface-facing terminals 116 of two adjacent semiconductor packages200 face one another. The main-surface-facing terminals 116 of twoadjacent semiconductor packages 200 are electrically connected to oneanother by a direct electrical connection 306. This arrangement providesfor electrical interconnections that are above the printed circuit board302, thus alleviating the demand for interconnection capacity of theconductive tracks within the printed circuit board.

Terms such as “first”, “second”, and the like, are used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having”, “containing”, “including”,“comprising” and the like are open ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a”, “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A packaged semiconductor device, comprising: asemiconductor die comprising a plurality of bond pads; an encapsulantbody of electrically insulating encapsulant material that encapsulatesthe semiconductor die; a plurality of sidewall-facing terminals disposedon a sidewall of the encapsulant body, wherein the sidewall-facingterminal is electrically connected to one of the bond pads; wherein thesidewall-facing terminal extends completely between top and bottomsurfaces of the encapsulant body, and wherein the electricallyinsulating encapsulant material comprises a laser activatable moldcompound.
 2. The packaged semiconductor device of claim 1, wherein eachof the sidewall-facing terminals continuously extend from the sidewallof the encapsulant body to a main surface of the encapsulant body thatintersects with the sidewall of the encapsulant body.
 3. The packagedsemiconductor device of claim 2, wherein the packaged semiconductordevice comprises a notch in the sidewall of the encapsulant body thatextends between the top and bottom surfaces, and wherein each of thesidewall-facing terminals is disposed within the notch.
 4. The packagedsemiconductor device of claim 1, wherein the packaged semiconductordevice is configured as an integrated circuit.
 5. The packagedsemiconductor device of claim 1, wherein the encapsulant body comprisesa first mold compound material that encapsulates the semiconductor die,and wherein the laser-activatable mold compound is formed on the firstmold compound material such that the laser-activatable mold compound isexposed at outer surfaces of the encapsulant body.
 6. The packagedsemiconductor device of claim 1, wherein a rear surface of thesemiconductor die is exposed at the bottom surface of the encapsulantbody.
 7. The packaged semiconductor device of claim 1, wherein a rearsurface of the semiconductor die is covered by the encapsulant body. 8.The packaged semiconductor device of claim 1, wherein the sidewall ofthe encapsulant body outside of each of the sidewall-facing terminals issubstantially coplanar to each of the sidewall-facing terminals.
 9. Thepackaged semiconductor device of claim 1, wherein each of thesidewall-facing terminals is formed on a laser activated region of thelaser activatable mold compound.
 10. The packaged semiconductor deviceof claim 9, wherein the sidewall of the encapsulant body between pairsof the sidewall-facing terminals is not laser activated.